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CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features
Functional Description
The CY7C1012DV33 is a high performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE1, CE2, and CE3). CE1 controls the data on the IO0 - IO7, while CE2 controls the data on IO8 - IO15, and CE3 controls the data on the data pins IO16 - IO23. This device has an automatic power down feature that significantly reduces power consumption when deselected. Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input and output (IO) pins is then written into the location specified on the address pins (A0 - A18). Asserting all of the chip selects LOW and write enable LOW writes all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. Data bytes are also individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH, while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins appear on the specified data input and output (IO) pins. Asserting all the chip selects LOW reads all 24 bits of data from the SRAM. The 24 IO pins (IO0 - IO23) are placed in a high impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For more information, see the Truth Table on page 8.
High speed tAA = 8 ns Low active power ICC = 225 mA at 8 ns Low CMOS standby power ISB2 = 25 mA Operating voltages of 3.3 0.3V 2.0V data retention Automatic power down when deselected TTL compatible inputs and outputs Available in Pb-free standard 119-Ball PBGA

Logic Block Diagram
INPUT BUFFER
ROW DECODER
A(9:0)
512K x 24 ARRAY
SENSE AMPS
IO0 - IO7 IO8 - IO15 IO16 - IO23
COLUMN DECODER
CONTROL LOGIC
CE1, CE2, CE3 WE OE
A(18:10)
Cypress Semiconductor Corporation Document Number: 38-05610 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 10, 2007
CY7C1012DV33
Selection Guide
-8 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 8 225 25 Unit ns mA mA
Pin Configurations
Figure 1. 119-Ball PBGA (Top View) [1]
1 A B C D E F G H J K L M N P R T U NC NC IO12 IO13 IO14 IO15 IO16 IO17 NC IO18 IO19 IO20 IO21 IO22 IO23 NC NC
2 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
3 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A
4 A CE1 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE
5 A A CE3 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A
6 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
7 NC NC IO0 IO1 IO2 IO3 IO4 IO5 NC IO6 IO7 IO8 IO9 IO10 IO11 NC NC
Note 1. NC pins are not connected on the die.
Document Number: 38-05610 Rev. *C
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CY7C1012DV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND [2] ....-0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State [2] .................................. -0.5V to VCC + 0.5V DC Input Voltage
[2]
Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............. ...............................>2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V 0.3V
............................... -0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL[2] IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VOUT < VCC, output disabled VCC = Max, f = fMAX = 1/tRC IOUT = 0 mA CMOS levels Test Conditions [3] Min VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA 2.0 -0.3 -1 -1 2.4 0.4 VCC + 0.3 0.8 +1 +1 225 30 25 -8 Max Unit V V V V A A mA mA mA
Automatic CE Power Down Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Current --TTL Inputs Automatic CE Power Down Max VCC, CE > VCC - 0.3V, Current --CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
Notes 2. VIL (min) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1, CE2 , and CE3 LOW. When HIGH, CE indicates the CE1 ,CE2 , or CE3 is HIGH.
Document Number: 38-05610 Rev. *C
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CY7C1012DV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance IO Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 8 10 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (junction to ambient) Thermal Resistance (junction to case) Test Conditions Still air, soldered on a 3 x 4.5 inch, four layer printed circuit board 119-Ball PBGA 20.31 8.35 Unit C/W C/W
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows. [4]
OUTPUT Z0 = 50
50 30 pF*
VTH = 1.5V
3.3V OUTPUT 5 pF* *Including jig and scope
R1 317
R2 351 (b)
(a) *Capacitive Load consists of all components of the test environment
3.0V GND All input pulses 90% 10% (c) 90% 10%
Rise Time > 1V/ns
Fall Time:> 1V/ns
Note 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
Document Number: 38-05610 Rev. *C
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CY7C1012DV33
AC Switching Characteristics
Over the Operating Range [5] Parameter Read Cycle tpower [6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle [9, 10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE Active LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[7] [7] [3]
Description
-8 Min 100 8 8 3 8 5 1 5 3 5 0 Max
Unit
VCC(Typical) to the First Access Read Cycle Time Address to Data Valid Data Hold from Address Change CE Active LOW to Data Valid [3] OE LOW to Data Valid OE LOW to Low Z
[7] [7]
s ns ns ns ns ns ns ns ns ns ns 8 ns ns ns ns ns ns ns ns ns ns 5 ns
OE HIGH to High Z
CE Active LOW to Low Z [3, 7] CE Deselect HIGH to High Z CE Active LOW to Power Up
[3, 7] [3, 8] [3, 8]
CE Deselect HIGH to Power Down
8 6 6 0 0 6 5 0 3
Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of AC Test Loads and Waveforms, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 200 mV from steady state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE1 or CE2 or CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05610 Rev. *C
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CY7C1012DV33
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR [11] tR [12] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions [3] Min 2 25 Typ Max Unit V mA ns ns
Data Retention Waveform
DATA RETENTION MODE
VCC
CE
3.0V tCDR
VDR > 2V
3.0V tR
Switching Waveforms
Figure 2. Read Cycle No. 1 [13, 14]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 3. Read Cycle No. 2 (OE Controlled) [3, 14, 15]
ADDRESS tRC CE tACE OE tDOE tLZOE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Notes 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE transition LOW.
Document Number: 38-05610 Rev. *C
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CY7C1012DV33
Switching Waveforms
(continued) Figure 4. Write Cycle No. 1 (CE Controlled) [3, 16, 17]
tWC
ADDRESS tSCE CE tSA tAW WE tPWE tSD DATA IO DATA VALID tHD tSCE tHA
Figure 5. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tHZOE DATA IO NOTE 18 tSD DATAIN VALID tHD
Figure 6. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]
tWC ADDRESS tSCE CE tAW tSA WE tSD DATA IO NOTE 18 tHZWE
Notes 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 18. During this period, the IOs are in output state. Do not apply input signals.
tHA tPWE
tHD
DATA VALID tLZWE
Document Number: 38-05610 Rev. *C
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CY7C1012DV33
Truth Table
CE1 H L H H L L H H L L CE2 H H L H L H L H L L CE3 H H H L L H H L L L OE X L L L L X X X X H WE X H H H H L L L L H IO0 - IO7 High Z Data Out High Z High Z Full Data Out Data In High Z High Z Full Data In High Z IO8 - IO15 High Z High Z Data Out High Z Full Data Out High Z Data In High Z Full Data In High Z IO16 - IO23 High Z High Z High Z Data Out Full Data Out High Z High Z Data In Full Data In High Z Read Read Read Read Write Write Write Write Mode Power Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Selected, Active (ICC) Outputs Disabled
Document Number: 38-05610 Rev. *C
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CY7C1012DV33
Ordering Information
Speed (ns) 8 Ordering Code CY7C1012DV33-8BGXC Package Name 51-85115 Package Type 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Operating Range Commercial
Package Diagram
Figure 7. 119-Ball PBGA (14 x 22 x 2.4 mm)
51-85115-*B
Document Number: 38-05610 Rev. *C
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CY7C1012DV33
Document History Page
Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM Document Number: 38-05610 REV. ** *A ECN NO. 250650 469517 Issue Date See ECN See ECN Orig. of Change SYT NXR New datasheet Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed -10 and -12 speed bins from product offering Changed J7 Ball of BGA from DNU to NC Removed Industrial Operating range from product offering Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page 3 Changed ICC(Max) from 220 mA to 150 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot specification in footnote 1 Updated the Truth Table Updated the Ordering Information table Added note 1 for NC pins Changed ICC specification from 150 mA to 185 mA Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, and tSCE in AC Switching Characteristics Table on page 4 Converted from preliminary to final Updated block diagram Changed ICC specification from 185 mA to 225 mA Updated thermal specs Description of Change
*B
499604
See ECN
NXR
*C
1462585 See ECN
VKN
(c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05610 Rev. *C
Revised September 10, 2007
Page 10 of 10
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